The invention is in the field of power supply regulation circuits, and relates more particularly to an improved sample-and-hold circuit for a switched-mode power supply.
Switched-mode power supplies are well known in the art, and are typically used to obtain good regulation (due to switched feedback) as well as efficient and economical filtering, since smaller-value filtering components can be used because of the typically high operating frequency of the switched-mode supply.
One technique used for obtaining good regulation in switched-mode power supplies is to employ a sample-and-hold circuit in a closed-loop feedback mode. One such circuit is disclosed in European Patent Application No. 97200855.1, filed on Mar. 21, 1997, corresponding to U.S. patent application Ser. No. 08/927,831 filed on Sep. 11, 1997 and to be incorporated herein by reference in its entirety. It is noted that the foregoing is not deemed to be prior art, but is discussed herein as background in that the present invention provides an improvement thereover. In this sample-and-hold circuit, the voltage on a primary auxiliary winding, which is a representation of the output voltage, is sampled, and the sampled voltage is stored in an off-chip sample-and-hold capacitor. The sampled voltage is used to set the duty cycle of operation for a switching transistor coupled in series with a primary transformer winding by providing a pulse-width modulated signal to the switching transistor.
This type of sample-and-hold regulation scheme provides excellent regulation, but suffers from the serious drawback that at or above a certain voltage level on the capacitor, the duty cycle of the pulse-width-modulation signal can drop to zero and the system can go out of regulation, with the feedback loop open. Such a "stuck" state can occur, for example, if the output voltage of the system rises well beyond its nominal value, such as may occur at startup or during a voltage spike or fault condition.
Once such a condition occurs, the duty cycle of the pulse-width-modulation signal will be driven to zero and no switching regulation will occur. This "stuck" state will continue until the sample-and-hold capacitor discharges to a sufficiently low voltage such that the duty cycle of the pulse-width-modulation signal is greater than zero, whereupon the system will revert to its normal closed-loop feedback mode of operation. Thus, under certain conditions, the foregoing sample-and-hold regulation scheme may effectively become disabled for an indeterminate and possibly an unsatisfactorily long period of time.
Accordingly, it would be desirable to have a sample-and-hold circuit for a switched-mode power supply in which a "stuck" or open-loop mode of operation can be detected, and in which the normal closed-loop feedback mode of operation can be efficiently restored in a controlled and timely manner.